Microelectronics typically involve the use of thin semiconductor materials such as silicon wafers that may be formed into individual units. Such elements are often used in integrated circuits (ICs) that may be subsequently installed onto printed circuit boards (PCBs). The field of Microelectronics has rapidly expanded over the last few decades with a demand for greater storage or memory capacity and decreased size. Additionally, cost reduction is a continual concern that greatly influences the development of new microelectronic technologies and procedures.
The demand for consumer products and applications for higher performance, higher capacity and lower cost has driven the demand for smaller, more capable microelectronic components. Such increased demand for smaller sizes has led to the development of 3D stacking. 3D-Stacking typically involves the stacking of microelectronic components in a vertical fashion and applying vertical interconnections between the layers. Traditionally vertical interconnection methods have included through-silicon vias (TSVs), wire bonding, and flip chip methods that have enabled manufactures to produce ICs that have greater capacity and a smaller footprint.
With the increase in demand for smaller size and greater capacity the balance of performance, capacity, and cost is the challenge in the development of microelectronic components. The current methods used for stacking and bonding have increased in cost due to the increase in time of manufacture and cost of materials used.